AD9269BCPZ-20

Product Summary

The AD9269BCPZ-20 is a monolithic, dual-channel, 1.8 V supply, 16-bit,20/40/65/80 MSPS analog-to-digital converter (ADC). It featuresa high performance sample-and-hold circuit and on-chip voltagereference.The product uses multistage differential pipeline architecture withoutput error correction logic to provide 16-bit accuracy at 80 MSPSdata rates and to guarantee no missing codes over the full operatingtemperature range. The applications of the AD9269BCPZ-20 include Communications, Diversity radio systems, Multimode digital receivers, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA, I/Q demodulation systems, Smart antenna systems, Battery-powered instruments, Handheld scope meters, Portable medical imaging, Ultrasound, Radar/LIDAR.

Parametrics

AD9269BCPZ-20 absolute maximum ratings: (1)AVDD to AGND: -0.3 V to +2.0 V; (2)DRVDD to AGND: -0.3 V to +3.9 V; (3)VIN+A, VIN+B, VIN-A, VIN-B to AGND: -0.3 V to AVDD + 0.2 V; (4)CLK+, CLK- to AGND: -0.3 V to AVDD + 0.2 V; (5)SYNC to AGND: -0.3 V to DRVDD + 0.3 V; (6)VREF to AGND: -0.3 V to AVDD + 0.2 V; (7)SENSE to AGND: -0.3 V to AVDD + 0.2 V; (8)VCM to AGND: -0.3 V to AVDD + 0.2 V; (9)RBIAS to AGND: -0.3 V to AVDD + 0.2 V; (10)CSB to AGND: -0.3 V to DRVDD + 0.3 V; (11)SCLK/DFS to AGND: -0.3 V to DRVDD + 0.3 V; (12)SDIO/DCS to AGND: -0.3 V to DRVDD + 0.3 V; (13)OEB to AGND: -0.3 V to DRVDD + 0.3 V; (14)PDWN to AGND: -0.3 V to DRVDD + 0.3 V; (15)D0x through D15x to AGND: -0.3 V to DRVDD + 0.3 V; (16)DCOx to AGND: -0.3 V to DRVDD + 0.3 V; (17)Operating Temperature Range (Ambient): -40℃ to +85℃; (18)Maximum Junction Temperature Under Bias: 150℃; (19)Storage Temperature Range (Ambient): -65℃ to +150℃.

Features

AD9269BCPZ-20 features: (1)1.8 V analog supply operation; (2)1.8 V to 3.3 V output supply; (3)Integrated quadrature error correction (QEC), SNR, 77.6 dBFS at 9.7 MHz input; 71 dBFS at 200 MHz input; SFDR, 93 dBc at 9.7 MHz input; 80 dBc at 200 MHz input; Low power, 44 mW per channel at 20 MSPS; 100 mW per channel at 80 MSPS; (4)Differential input with 700 MHz bandwidth; (5)On-chip voltage reference and sample-and-hold circuit; (6)2 V p-p differential analog input; (7)DNL = -0.5/+1.1 LSB; (8)Serial port control options, Offset binary, gray code, or twos complement data format; Optional clock duty cycle stabilizer (DCS)Integer 1-to-6 input clock divider; Data output multiplex option; Built-in selectable digital test pattern generation; Energy-saving power-down modes; Data clock output (DCO) with programmable clock anddata alignment.

Diagrams