Product Summary
The CY7C1350G-133AXC is a 3.3V, 128K × 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G-133AXC is equipped with the advanced No Bus Latency (NoBL) logic required to enable consec- utive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.
Parametrics
CY7C1350G-133AXC absolute maximum ratings: (1)Storage Temperature: -65 to +150℃; (2)Ambient Temperature with Power Applied: -55 to +125℃; (3)Supply Voltage on VDD Relative to GND: -0.5V to +4.6V; (4)DC Voltage Applied to Outputs in tri-state: -0.5V to VDDQ + 0.5V; (5)DC Input Voltage: -0.5V to VDD + 0.5V; (6)Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage:> 2001V; (8)Latch-up Current: > 200 mA.
Features
CY7C1350G-133AXC features: (1)Pin compatible and functionally equivalent to ZBT devices ; (2)Internally self-timed output buffer control to eliminate the need to use OE; (3)Byte Write capability; (4)128K x 36 common I/O architecture ; (5)Single 3.3V power supply; (6)2.5V/3.3V I/O Operation; (7)Fast clock-to-output times; (8)Clock Enable (CEN) pin to suspend operation; (9)Synchronous self-timed writes; (10)Asynchronous output enable (OE); (11)Lead-Free 100 TQFP and 119 BGA packages; (12)Burst Capability-linear or interleaved burst order; (13)?ZZ Sleep mode option.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
Quantity | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CY7C1350G-133AXC |
Cypress Semiconductor |
SRAM 128Kx36 3.3V NoBL Sync PL SRAM COM |
Data Sheet |
|
|
|||||||||||||
CY7C1350G-133AXCT |
Cypress Semiconductor |
SRAM 128Kx36 3.3V NoBL Sync PL SRAM COM |
Data Sheet |
|
|