HD64F2329BVF25

Product Summary

The HD64F2329BVF25 is a member of H8S/2329 Group, which are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting functions of HD64F2329BVF25 required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.

Parametrics

HD64F2329BVF25 absolute maximum ratings:(1)Power supply voltage, VCC: –0.3 to +4.6 V; (2)Input voltage (except port 4), Vin: –0.3 to VCC +0.3 V; (3)Input voltage (port 4), Vin: –0.3 to AVCC +0.3 V; (4)Reference power supply voltage, Vref: –0.3 to AVCC +0.3 V; (5)Analog power supply voltage, AVCC: –0.3 to +4.6 V; (6)Analog input voltage, VAN: –0.3 to AVCC +0.3 V; (7)Operating temperature, Topr: Regular specifications: –20 to +75 ℃; (8)Wide-range specifications: –40 to +85 ℃; (9)Storage temperature, Tstg: –55 to +125 ℃.

Features

HD64F2329BVF25 features: (1)General-register machine; (2)High-speed operation suitable for realtime control; (3)Instruction set suitable for high-speed operation; (4)CPU operating mode; (5)Address space divided into 8 areas, with bus specifications settable independently for each area; (6)Chip select output possible for each area; (7)Choice of 8-bit or 16-bit access space for each area; (8)2-state or 3-state access space can be designated for each area; (9)Number of program wait states can be set for each area; (10)Burst ROM directly connectable; (11)Maximum 8-Mbyte DRAM directly connectable (or use of interval timer possible); (12)External bus release function DMA controller (DMAC); (13)Choice of short address mode.

Diagrams