SST89E564RD-40-C-NJ

Product Summary

The SST89E564RD-40-C-NJ is a member of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. It uses the 8051 instruction set. It also comes with 72/40 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. In addition to the 72/40 KByte of EEPROM on-chip program memory and 1024 x8 bits of on-chip RAM, the SST89E564RD-40-C-NJ can address up to 64 KByte of external program memory and up to 64 KByte of external RAM.

Parametrics

SST89E564RD-40-C-NJ absolute maximum stress ratings:(1)Ambient Temperature Under Bias:-55℃ to +125℃; (2)Storage Temperature:-65℃ to +150℃; (3)Voltage on EA# Pin to VSS:-0.5V to +14.0V; (4)D.C. Voltage on Any Pin to Ground Potential:-0.5V to VDD+0.5V; (5)Transient Voltage (<20ns) on Any Other Pin to VSS: -1.0V to VDD+1.0V; (6)Maximum IOL per I/O Pins P1.5, P1.6, P1.7:20mA; (7)Maximum IOL per I/O for All Other Pins:15mA; (8)Package Power Dissipation Capability (TA = 25℃):1.5W; (9)Through Hole Lead Soldering Temperature (10 Seconds):300℃; (10)Surface Mount Solder Reflow Temperature:: “with-Pb” units1: 240℃ for 3 seconds:“non-Pb” units: 260℃ for 3 seconds; (11)Output Short Circuit Current2:50 mA.

Features

SST89E564RD-40-C-NJ features:(1)8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory:fully software compatible;development toolset compatible;pin-for-pin package compatible; (2)sst89e564rd/sst89e554rc operation:0 to 40 mhz at 5v; (3)sst89v564rd/sst89v554rc operation:0 to 33 mhz at 3v; (4)total 1 kbyte internal ram (256 byte + 768 byte); (5)dual block superflash eeprom:sst89e564rd/sst89v564rd:64 kbyte primary block + 8 kbyte secondary block (128-byte sector size for both blocks); – sst89e554rc/sst89v554rc:32 kbyte primary block + 8 kbyte secondary block (128-byte sector size for both blocks);individual block security lock with softlock; concurrent operation during in-application programming (iap); memory overlay for interrupt support during iap; (6)support external address range up to 64 kbyte of program and data memory; (7)three high-current drive port 1 pins; (8)three 16-bit timers/counters; (9)full-duplex, enhanced uart:framing error detection;automatic address recognition; (10)eight interrupt sources at 4 priority levels; (11)programmable watchdog timer (wdt); (12)programmable counter array (pca); (13)four 8-bit i/o ports (32 i/o pins); (14)second dptr register; (15)low emi mode (inhibit ale); (16)spi serial interface; (17)standard 12 clocks per cycle, the device has an option to double the speed to 6 clocks per cycle.; (18)ttl- and cmos-compatible logic levels; (19)brown-out detection; (20)low power modes:power-down mode with external interrupt wake-up;idle mode; (21)temperature ranges:commercial (0℃ to +70℃);industrial (-40℃ to +85℃); (22)packages available:40-contact wqfn;44-lead plcc; 40-pin pdip (port 4 feature not available); 44-lead tqfp;non-pb (lead-free) packages available.

Diagrams